
`timescale 1ns/1ns

module counter(clock,clear,count_enable,Q);
input clock,clear;
input count_enable;
output [3:0] Q;

wire a1,a2,a3;

assign a1=Q[0]&count_enable;
assign a2=Q[1]&a1;
assign a3=Q[2]&a2;

master_slave_jk jk0(count_enable,count_enable,clear,clock,Q[0],);


master_slave_jk jk1(a1,a1,clear,clock,Q[1],);

master_slave_jk jk2(a2,a2,clear,clock,Q[2],);

master_slave_jk jk3(a3,a3,clear,clock,Q[3],);


endmodule 

module master_slave_jk(J,K,clear,clock,
                       q,qbar);
input J,K;
input clear,clock;
output q,qbar;
wire a,b,y,ybar,c,d;

assign #1 a=~(qbar&J&clear&clock),
       b=~(q&clock&K);
assign #1 y=~(a&ybar),
       ybar=~(y&b&clear);
assign #1 c=~(y&(~clock)),
       d=~(ybar&(~clock));
assign #1 q=~(c&qbar),
       qbar=~(d&q&clear);

endmodule

